/*---------------------------------------------------------------------
 * File name: registers.h
 *
 * Copyright (c) <2020-2022>, <ChenLong>
 *
 * All rights reserved.
 *
 * Author: ChenLong
 * Email: worldlong@foxmail.com
 *--------------------------------------------------------------------*/
#pragma once
#include <stdint.h>
/*
All registers are 16 bits
*/
//cmd definition 
#define CMD_SYSTEM_RESET                 (uint32_t)(1 << 0)
#define CMD_FAULT_RESET                  (uint32_t)(1 << 1)
#define CMD_STOP                         (uint32_t)(1 << 2)
#define CMD_LVOL_ON                      (uint32_t)(1 << 3)
#define CMD_LVOL_OFF                     (uint32_t)(1 << 4)
#define CMD_HVOL_ON                      (uint32_t)(1 << 5)
#define CMD_HVOL_OFF                     (uint32_t)(1 << 6)
#define CMD_TRIG_ON                      (uint32_t)(1 << 7)
#define CMD_TRIG_OFF                     (uint32_t)(1 << 8)
#define CMD_TRIG_INT                     (uint32_t)(1 << 9)
#define CMD_TRIG_EXT                     (uint32_t)(1 << 10)
#define CMD_FAULT_ON                     (uint32_t)(1 << 11)
#define CMD_FAULT_OFF                    (uint32_t)(1 << 12)
#define CMD_READY_SET                    (uint32_t)(1 << 13)
#define CMD_READY_RESET                  (uint32_t)(1 << 14)
#define CMD_PARAM_RESET                  (uint32_t)(1 << 15)
#define CMD_PARAM_SAVE                   (uint32_t)(1 << 16)
#define CMD_SWITCHBOX_RESET              (uint32_t)(1 << 17)

//fault mask  definition
#define FAULT_MASK_ALL                   (uint32_t)(1 << 0)
#define FAULT_MASK_SWITCHBOX             (uint32_t)(1 << 1)
#define FAULT_MASK_CHARGE_POWER          (uint32_t)(1 << 2)
#define FAULT_MASK_MMAG_POWER            (uint32_t)(1 << 3)
#define FAULT_MASK_CMAG_POWER            (uint32_t)(1 << 4)
#define FAULT_MASK_HEATER_POWER          (uint32_t)(1 << 5)
#define FAULT_MASK_WATER_OT              (uint32_t)(1 << 6)
#define FAULT_MASK_WATER_UF              (uint32_t)(1 << 7)

//status0 bit mask definition
#define STATUS0_LVOL_ON                  (uint32_t)(1 << 0)
#define STATUS0_READY                    (uint32_t)(1 << 1)
#define STATUS0_HVOL_ON                  (uint32_t)(1 << 2)
#define STATUS0_TRIG_ON                  (uint32_t)(1 << 3)
#define STATUS0_TRIG_SRC                 (uint32_t)(1 << 4)
#define STATUS0_LOCK_FAULT               (uint32_t)(1 << 5)
#define STATUS0_FAULT                    (uint32_t)(1 << 6)
#define STATUS0_FAULT_SWITCHBOX1         (uint32_t)(1 << 7)
#define STATUS0_FAULT_SWITCHBOX2         (uint32_t)(1 << 8)
#define STATUS0_FAULT_SWITCHBOX3         (uint32_t)(1 << 9)
#define STATUS0_FAULT_MMAG_POWER         (uint32_t)(1 << 10)
#define STATUS0_FAULT_CMAG_POWER         (uint32_t)(1 << 11)
#define STATUS0_FAULT_BMAG_POWER         (uint32_t)(1 << 12)
#define STATUS0_FAULT_HEATER_POWER       (uint32_t)(1 << 13)
#define STATUS0_FAULT_CHARGE_POWER       (uint32_t)(1 << 14)
#define STATUS0_FAULT_PUMP_UV            (uint32_t)(1 << 15)
#define STATUS0_FAULT_PUMP_OC            (uint32_t)(1 << 16)
#define STATUS0_FAULT_PULSE_UC           (uint32_t)(1 << 17)
#define STATUS0_FAULT_PULSE_OC           (uint32_t)(1 << 18)
#define STATUS0_FAULT_FIRE_OCT           (uint32_t)(1 << 19)
#define STATUS0_FAULT_WATER_UF           (uint32_t)(1 << 20)
#define STATUS0_FAULT_WATER_OT           (uint32_t)(1 << 21)
#define STATUS0_FAULT_HARD_STOP          (uint32_t)(1 << 22)
#define STATUS0_FAULT_SOFT_STOP          (uint32_t)(1 << 23)
#define STATUS0_FAULT_CTRL_KEY           (uint32_t)(1 << 24)
#define STATUS0_FAULT_USER_KEY           (uint32_t)(1 << 25)
#define STATUS0_FAULT_NOTRIG             (uint32_t)(1 << 26)
#define STATUS0_FAULT_REV1               (uint32_t)(1 << 27)
#define STATUS0_FAULT_REV2               (uint32_t)(1 << 28)
#define STATUS0_FAULT_REV3               (uint32_t)(1 << 29)

//status1 bit mask definition for switch box1
#define STATUS1_SWITCHBOX1_OFFLINE       (uint32_t)(1 << 0)
#define STATUS1_SWITCHBOX1_FAULT         (uint32_t)(1 << 1)
#define STATUS1_SWITCHBOX1_BLEED         (uint32_t)(1 << 2)
#define STATUS1_SWITCHBOX1_FAULT_OFF     (uint32_t)(1 << 3)
#define STATUS1_SWITCHBOX1_TRIG_SRC      (uint32_t)(1 << 4)
#define STATUS1_SWITCHBOX1_TRIG_ON       (uint32_t)(1 << 5)
#define STATUS1_SWITCHBOX1_WRITE_LOCK    (uint32_t)(1 << 6)
#define STATUS1_SWITCHBOX1_RESET         (uint32_t)(1 << 7)
#define STATUS1_SWITCHBOX1_PE1           (uint32_t)(1 << 8)
#define STATUS1_SWITCHBOX1_PE2           (uint32_t)(1 << 9)
#define STATUS1_SWITCHBOX1_PE3           (uint32_t)(1 << 10)
#define STATUS1_SWITCHBOX1_PE4           (uint32_t)(1 << 11)
#define STATUS1_SWITCHBOX1_PE5           (uint32_t)(1 << 12)
#define STATUS1_SWITCHBOX1_PE6           (uint32_t)(1 << 13)
#define STATUS1_SWITCHBOX1_OV1           (uint32_t)(1 << 14)
#define STATUS1_SWITCHBOX1_OV2           (uint32_t)(1 << 15)
#define STATUS1_SWITCHBOX1_OC1           (uint32_t)(1 << 16)
#define STATUS1_SWITCHBOX1_OC2           (uint32_t)(1 << 17)
#define STATUS1_SWITCHBOX1_OC3           (uint32_t)(1 << 18)
#define STATUS1_SWITCHBOX1_OC4           (uint32_t)(1 << 19)
#define STATUS1_SWITCHBOX1_OC5           (uint32_t)(1 << 20)
#define STATUS1_SWITCHBOX1_OC6           (uint32_t)(1 << 21)
#define STATUS1_SWITCHBOX1_OT            (uint32_t)(1 << 22)
#define STATUS1_SWITCHBOX1_UF            (uint32_t)(1 << 23)
#define STATUS1_SWITCHBOX1_UC1           (uint32_t)(1 << 24)
#define STATUS1_SWITCHBOX1_UC2           (uint32_t)(1 << 25)
#define STATUS1_SWITCHBOX1_UC3           (uint32_t)(1 << 26)
#define STATUS1_SWITCHBOX1_UC4           (uint32_t)(1 << 27)
#define STATUS1_SWITCHBOX1_UC5           (uint32_t)(1 << 28)
#define STATUS1_SWITCHBOX1_UC6           (uint32_t)(1 << 29)
#define STATUS1_SWITCHBOX1_FTIN          (uint32_t)(1 << 30)
#define STATUS1_SWITCHBOX1_NTFT          (uint32_t)(1 << 31)

//status2 bit mask definition for switch box2
#define STATUS2_SWITCHBOX2_OFFLINE       (uint32_t)(1 << 0)
#define STATUS2_SWITCHBOX2_FAULT         (uint32_t)(1 << 1)
#define STATUS2_SWITCHBOX2_BLEED         (uint32_t)(1 << 2)
#define STATUS2_SWITCHBOX2_FAULT_OFF     (uint32_t)(1 << 3)
#define STATUS2_SWITCHBOX2_TRIG_SRC      (uint32_t)(1 << 4)
#define STATUS2_SWITCHBOX2_TRIG_ON       (uint32_t)(1 << 5)
#define STATUS2_SWITCHBOX2_WRITE_LOCK    (uint32_t)(1 << 6)
#define STATUS2_SWITCHBOX2_RESET         (uint32_t)(1 << 7)
#define STATUS2_SWITCHBOX2_PE1           (uint32_t)(1 << 8)
#define STATUS2_SWITCHBOX2_PE2           (uint32_t)(1 << 9)
#define STATUS2_SWITCHBOX2_PE3           (uint32_t)(1 << 10)
#define STATUS2_SWITCHBOX2_PE4           (uint32_t)(1 << 11)
#define STATUS2_SWITCHBOX2_PE5           (uint32_t)(1 << 12)
#define STATUS2_SWITCHBOX2_PE6           (uint32_t)(1 << 13)
#define STATUS2_SWITCHBOX2_OV1           (uint32_t)(1 << 14)
#define STATUS2_SWITCHBOX2_OV2           (uint32_t)(1 << 15)
#define STATUS2_SWITCHBOX2_OC1           (uint32_t)(1 << 16)
#define STATUS2_SWITCHBOX2_OC2           (uint32_t)(1 << 17)
#define STATUS2_SWITCHBOX2_OC3           (uint32_t)(1 << 18)
#define STATUS2_SWITCHBOX2_OC4           (uint32_t)(1 << 19)
#define STATUS2_SWITCHBOX2_OC5           (uint32_t)(1 << 20)
#define STATUS2_SWITCHBOX2_OC6           (uint32_t)(1 << 21)
#define STATUS2_SWITCHBOX2_OT            (uint32_t)(1 << 22)
#define STATUS2_SWITCHBOX2_UF            (uint32_t)(1 << 23)
#define STATUS2_SWITCHBOX2_UC1           (uint32_t)(1 << 24)
#define STATUS2_SWITCHBOX2_UC2           (uint32_t)(1 << 25)
#define STATUS2_SWITCHBOX2_UC3           (uint32_t)(1 << 26)
#define STATUS2_SWITCHBOX2_UC4           (uint32_t)(1 << 27)
#define STATUS2_SWITCHBOX2_UC5           (uint32_t)(1 << 28)
#define STATUS2_SWITCHBOX2_UC6           (uint32_t)(1 << 29)
#define STATUS2_SWITCHBOX2_FTIN          (uint32_t)(1 << 30)
#define STATUS2_SWITCHBOX2_NTFT          (uint32_t)(1 << 31)

//status3 bit mask definition for switch box3
#define STATUS3_SWITCHBOX3_OFFLINE       (uint32_t)(1 << 0)
#define STATUS3_SWITCHBOX3_FAULT         (uint32_t)(1 << 1)
#define STATUS3_SWITCHBOX3_BLEED         (uint32_t)(1 << 2)
#define STATUS3_SWITCHBOX3_FAULT_OFF     (uint32_t)(1 << 3)
#define STATUS3_SWITCHBOX3_TRIG_SRC      (uint32_t)(1 << 4)
#define STATUS3_SWITCHBOX3_TRIG_ON       (uint32_t)(1 << 5)
#define STATUS3_SWITCHBOX3_WRITE_LOCK    (uint32_t)(1 << 6)
#define STATUS3_SWITCHBOX3_RESET         (uint32_t)(1 << 7)
#define STATUS3_SWITCHBOX3_PE1           (uint32_t)(1 << 8)
#define STATUS3_SWITCHBOX3_PE2           (uint32_t)(1 << 9)
#define STATUS3_SWITCHBOX3_PE3           (uint32_t)(1 << 10)
#define STATUS3_SWITCHBOX3_PE4           (uint32_t)(1 << 11)
#define STATUS3_SWITCHBOX3_PE5           (uint32_t)(1 << 12)
#define STATUS3_SWITCHBOX3_PE6           (uint32_t)(1 << 13)
#define STATUS3_SWITCHBOX3_OV1           (uint32_t)(1 << 14)
#define STATUS3_SWITCHBOX3_OV2           (uint32_t)(1 << 15)
#define STATUS3_SWITCHBOX3_OC1           (uint32_t)(1 << 16)
#define STATUS3_SWITCHBOX3_OC2           (uint32_t)(1 << 17)
#define STATUS3_SWITCHBOX3_OC3           (uint32_t)(1 << 18)
#define STATUS3_SWITCHBOX3_OC4           (uint32_t)(1 << 19)
#define STATUS3_SWITCHBOX3_OC5           (uint32_t)(1 << 20)
#define STATUS3_SWITCHBOX3_OC6           (uint32_t)(1 << 21)
#define STATUS3_SWITCHBOX3_OT            (uint32_t)(1 << 22)
#define STATUS3_SWITCHBOX3_UF            (uint32_t)(1 << 23)
#define STATUS3_SWITCHBOX3_UC1           (uint32_t)(1 << 24)
#define STATUS3_SWITCHBOX3_UC2           (uint32_t)(1 << 25)
#define STATUS3_SWITCHBOX3_UC3           (uint32_t)(1 << 26)
#define STATUS3_SWITCHBOX3_UC4           (uint32_t)(1 << 27)
#define STATUS3_SWITCHBOX3_UC5           (uint32_t)(1 << 28)
#define STATUS3_SWITCHBOX3_UC6           (uint32_t)(1 << 29)
#define STATUS3_SWITCHBOX3_FTIN          (uint32_t)(1 << 30)
#define STATUS3_SWITCHBOX3_NTFT          (uint32_t)(1 << 31)

//status4 bit mask definition for heater power
#define STATUS4_HEATER_POWER_OFFLINE     (uint32_t)(1 << 0)
#define STATUS4_HEATER_POWER_AC          (uint32_t)(1 << 1)
#define STATUS4_HEATER_POWER_OTP         (uint32_t)(1 << 2)
#define STATUS4_HEATER_POWER_FLD         (uint32_t)(1 << 3)
#define STATUS4_HEATER_POWER_OVP         (uint32_t)(1 << 4)
#define STATUS4_HEATER_POWER_SO          (uint32_t)(1 << 5)
#define STATUS4_HEATER_POWER_OFF         (uint32_t)(1 << 6)
#define STATUS4_HEATER_POWER_INT         (uint32_t)(1 << 7)
#define STATUS4_HEATER_POWER_UVP         (uint32_t)(1 << 8)
#define STATUS4_HEATER_POWER_NU1         (uint32_t)(1 << 9)
#define STATUS4_HEATER_POWER_INPO        (uint32_t)(1 << 10)
#define STATUS4_HEATER_POWER_INTO        (uint32_t)(1 << 11)
#define STATUS4_HEATER_POWER_ITMO        (uint32_t)(1 << 12)
#define STATUS4_HEATER_POWER_ICOM        (uint32_t)(1 << 13)
#define STATUS4_HEATER_POWER_NU2         (uint32_t)(1 << 14)
#define STATUS4_HEATER_POWER_NU3         (uint32_t)(1 << 15)
#define STATUS4_HEATER_POWER_CV          (uint32_t)(1 << 16)
#define STATUS4_HEATER_POWER_CC          (uint32_t)(1 << 17)
#define STATUS4_HEATER_POWER_NFL         (uint32_t)(1 << 18)
#define STATUS4_HEATER_POWER_TW          (uint32_t)(1 << 19)
#define STATUS4_HEATER_POWER_AST         (uint32_t)(1 << 20)
#define STATUS4_HEATER_POWER_FBE         (uint32_t)(1 << 21)
#define STATUS4_HEATER_POWER_LSC         (uint32_t)(1 << 22)
#define STATUS4_HEATER_POWER_LOC         (uint32_t)(1 << 23)
#define STATUS4_HEATER_POWER_UVPEN       (uint32_t)(1 << 24)
#define STATUS4_HEATER_POWER_ILCEN       (uint32_t)(1 << 25)
#define STATUS4_HEATER_POWER_NU4         (uint32_t)(1 << 26)
#define STATUS4_HEATER_POWER_FBC         (uint32_t)(1 << 27)
#define STATUS4_HEATER_POWER_AVP         (uint32_t)(1 << 28)
#define STATUS4_HEATER_POWER_ACP         (uint32_t)(1 << 29)
#define STATUS4_HEATER_POWER_DWE         (uint32_t)(1 << 30)

//status5 bit mask definition for cmag power
#define STATUS5_CMAG_POWER_OFFLINE       (uint32_t)(1 << 0)
#define STATUS5_CMAG_POWER_AC            (uint32_t)(1 << 1)
#define STATUS5_CMAG_POWER_OTP           (uint32_t)(1 << 2)
#define STATUS5_CMAG_POWER_FLD           (uint32_t)(1 << 3)
#define STATUS5_CMAG_POWER_OVP           (uint32_t)(1 << 4)
#define STATUS5_CMAG_POWER_SO            (uint32_t)(1 << 5)
#define STATUS5_CMAG_POWER_OFF           (uint32_t)(1 << 6)
#define STATUS5_CMAG_POWER_INT           (uint32_t)(1 << 7)
#define STATUS5_CMAG_POWER_UVP           (uint32_t)(1 << 8)
#define STATUS5_CMAG_POWER_NU1           (uint32_t)(1 << 9)
#define STATUS5_CMAG_POWER_INPO          (uint32_t)(1 << 10)
#define STATUS5_CMAG_POWER_INTO          (uint32_t)(1 << 11)
#define STATUS5_CMAG_POWER_ITMO          (uint32_t)(1 << 12)
#define STATUS5_CMAG_POWER_ICOM          (uint32_t)(1 << 13)
#define STATUS5_CMAG_POWER_NU2           (uint32_t)(1 << 14)
#define STATUS5_CMAG_POWER_NU3           (uint32_t)(1 << 15)
#define STATUS5_CMAG_POWER_CV            (uint32_t)(1 << 16)
#define STATUS5_CMAG_POWER_CC            (uint32_t)(1 << 17)
#define STATUS5_CMAG_POWER_NFL           (uint32_t)(1 << 18)
#define STATUS5_CMAG_POWER_TW            (uint32_t)(1 << 19)
#define STATUS5_CMAG_POWER_AST           (uint32_t)(1 << 20)
#define STATUS5_CMAG_POWER_FBE           (uint32_t)(1 << 21)
#define STATUS5_CMAG_POWER_LSC           (uint32_t)(1 << 22)
#define STATUS5_CMAG_POWER_LOC           (uint32_t)(1 << 23)
#define STATUS5_CMAG_POWER_UVPEN         (uint32_t)(1 << 24)
#define STATUS5_CMAG_POWER_ILCEN         (uint32_t)(1 << 25)
#define STATUS5_CMAG_POWER_NU4           (uint32_t)(1 << 26)
#define STATUS5_CMAG_POWER_FBC           (uint32_t)(1 << 27)
#define STATUS5_CMAG_POWER_AVP           (uint32_t)(1 << 28)
#define STATUS5_CMAG_POWER_ACP           (uint32_t)(1 << 29)
#define STATUS5_CMAG_POWER_DWE           (uint32_t)(1 << 30)

//status6 bit mask definition for mmag power
#define STATUS6_MMAG_POWER_ST0           (uint32_t)(1 << 0)
#define STATUS6_MMAG_POWER_ST1           (uint32_t)(1 << 1)
#define STATUS6_MMAG_POWER_ST2           (uint32_t)(1 << 2)
#define STATUS6_MMAG_POWER_ST3           (uint32_t)(1 << 3)
#define STATUS6_MMAG_POWER_ST4           (uint32_t)(1 << 4)
#define STATUS6_MMAG_POWER_ST5           (uint32_t)(1 << 5)
#define STATUS6_MMAG_POWER_ST6           (uint32_t)(1 << 6)
#define STATUS6_MMAG_POWER_ST7           (uint32_t)(1 << 7)
#define STATUS6_MMAG_POWER_OFFLINE       (uint32_t)(1 << 8)
#define STATUS6_MMAG_POWER_ST9           (uint32_t)(1 << 9)
#define STATUS6_MMAG_POWER_ST10          (uint32_t)(1 << 10)
#define STATUS6_MMAG_POWER_ST11          (uint32_t)(1 << 11)
#define STATUS6_MMAG_POWER_ST12          (uint32_t)(1 << 12)
#define STATUS6_MMAG_POWER_ST13          (uint32_t)(1 << 13)
#define STATUS6_MMAG_POWER_ST14          (uint32_t)(1 << 14)
#define STATUS6_MMAG_POWER_ST15          (uint32_t)(1 << 15)
#define STATUS6_MMAG_POWER_OUC           (uint32_t)(1 << 16)
#define STATUS6_MMAG_POWER_OOC           (uint32_t)(1 << 17)
#define STATUS6_MMAG_POWER_OOV           (uint32_t)(1 << 18)
#define STATUS6_MMAG_POWER_DCCT          (uint32_t)(1 << 19)
#define STATUS6_MMAG_POWER_DCSFT         (uint32_t)(1 << 20)
#define STATUS6_MMAG_POWER_OT            (uint32_t)(1 << 21)
#define STATUS6_MMAG_POWER_LPFT          (uint32_t)(1 << 22)
#define STATUS6_MMAG_POWER_PE            (uint32_t)(1 << 23)
#define STATUS6_MMAG_POWER_NU1           (uint32_t)(1 << 24)
#define STATUS6_MMAG_POWER_NU2           (uint32_t)(1 << 25)
#define STATUS6_MMAG_POWER_BP            (uint32_t)(1 << 26)
#define STATUS6_MMAG_POWER_IUV           (uint32_t)(1 << 27)
#define STATUS6_MMAG_POWER_IOV           (uint32_t)(1 << 28)
#define STATUS6_MMAG_POWER_INFT1         (uint32_t)(1 << 29)
#define STATUS6_MMAG_POWER_INFT2         (uint32_t)(1 << 30)
#define STATUS6_MMAG_POWER_SDFT          (uint32_t)(1 << 31)

//status7 bit mask definition for charge power
#define STATUS7_CHARGE_POWER_LV          (uint32_t)(1 << 0)
#define STATUS7_CHARGE_POWER_READY       (uint32_t)(1 << 1)
#define STATUS7_CHARGE_POWER_HV          (uint32_t)(1 << 2)
#define STATUS7_CHARGE_POWER_LOCAL       (uint32_t)(1 << 3)
#define STATUS7_CHARGE_POWER_FAULT       (uint32_t)(1 << 4)
#define STATUS7_CHARGE_POWER_SAFETY      (uint32_t)(1 << 5)
#define STATUS7_CHARGE_POWER_IGBT_OC     (uint32_t)(1 << 6)
#define STATUS7_CHARGE_POWER_OV          (uint32_t)(1 << 7)
#define STATUS7_CHARGE_POWER_OT          (uint32_t)(1 << 8)
#define STATUS7_CHARGE_POWER_WATER       (uint32_t)(1 << 9)
#define STATUS7_CHARGE_POWER_LACK        (uint32_t)(1 << 10)
#define STATUS7_CHARGE_POWER_FAN         (uint32_t)(1 << 11)
#define STATUS7_CHARGE_POWER_OC          (uint32_t)(1 << 12)
#define STATUS7_CHARGE_POWER_SLAVE       (uint32_t)(1 << 13)
#define STATUS7_CHARGE_POWER_INHIBIT     (uint32_t)(1 << 14)
#define STATUS7_CHARGE_POWER_VMODE       (uint32_t)(1 << 15)
#define STATUS7_CHARGE_POWER_CMODE       (uint32_t)(1 << 16)
#define STATUS7_CHARGE_POWER_EOC         (uint32_t)(1 << 17)
#define STATUS7_CHARGE_POWER_CTTR        (uint32_t)(1 << 18)
#define STATUS7_CHARGE_POWER_OFFLINE     (uint32_t)(1 << 19)

/*********************************************
 *       registers definition
 *********************************************/
/*---------nvd registers start-----------*/
#define NVD_REG_START                    0
/* magic registers group */
#define MAGIC_REG_START                  0
#define REG_MAGIC_ID_L                   0
#define REG_MAGIC_ID_H                   1
#define MAGIC_REG_END                    1
/* config registers group */
#define CONFIG_REG_START                 2
#define REG_CONFIG_ETH_HOSTIP_L          2
#define REG_CONFIG_ETH_HOSTIP_H          3
#define REG_CONFIG_ETH_GATEWAY_L         4
#define REG_CONFIG_ETH_GATEWAY_H         5
#define REG_CONFIG_ETH_MASK_L            6
#define REG_CONFIG_ETH_MASK_H            7
#define REG_CONFIG_TCP_CLIENT_RIP_L      8
#define REG_CONFIG_TCP_CLIENT_RIP_H      9
#define REG_CONFIG_TCP_CLIENT_RPORT      10
#define REG_CONFIG_TCP_CLIENT_LPORT      11
#define REG_CONFIG_TCP_SERVER_LPORT      12
#define REG_CONFIG_RS4851_L              13
#define REG_CONFIG_RS4851_H              14
#define REG_CONFIG_RS4852_L              15
#define REG_CONFIG_RS4852_H              16
#define REG_CONFIG_MODBUS_ID             17
#define CONFIG_REG_END                   17
/* param registers group */
#define PARAM_REG_START                  18
#define REG_PARAM_DS18B20_0_ROM_0        18
#define REG_PARAM_DS18B20_0_ROM_1        19
#define REG_PARAM_DS18B20_0_ROM_2        20
#define REG_PARAM_DS18B20_0_ROM_3        21
#define REG_PARAM_DS18B20_1_ROM_0        22
#define REG_PARAM_DS18B20_1_ROM_1        23
#define REG_PARAM_DS18B20_1_ROM_2        24
#define REG_PARAM_DS18B20_1_ROM_3        25
#define REG_PARAM_DS18B20_2_ROM_0        26
#define REG_PARAM_DS18B20_2_ROM_1        27
#define REG_PARAM_DS18B20_2_ROM_2        28
#define REG_PARAM_DS18B20_2_ROM_3        29
#define REG_PARAM_DS18B20_3_ROM_0        30
#define REG_PARAM_DS18B20_3_ROM_1        31
#define REG_PARAM_DS18B20_3_ROM_2        32
#define REG_PARAM_DS18B20_3_ROM_3        33
#define REG_PARAM_IN_PIN_REV             34
#define REG_PARAM_OUT_PIN_REV            35
#define REG_PARAM_PULSE_VOL              36   //0.1kV
#define REG_PARAM_PULSE_WIDTH            37   //0.1us
#define REG_PARAM_PULSE_FREQ             38   //1Hz
#define REG_PARAM_HEATER_CUR             39   //0.1A
#define REG_PARAM_MMAG_CUR               40   //0.1A
#define REG_PARAM_CMAG_CUR               41   //0.1A
#define REG_PARAM_HEATER_RATE            42   //0.01A/s
#define REG_PARAM_TRIG_DELAY             43   //0.1us
#define REG_PARAM_PREHEAT_TIME           44   //sec
#define REG_PARAM_WATER_TTHR             45   //0.01deg
#define REG_PARAM_WATER_FTHR             46   //0.01L/min
#define REG_PARAM_FIRE_CTHR              47
#define REG_PARAM_HVOL_TCT_L             48   //sec
#define REG_PARAM_HVOL_TCT_H             49   //sec
#define REG_PARAM_LVOL_TCT_L             50   //sec
#define REG_PARAM_LVOL_TCT_H             51   //sec
#define REG_PARAM_TRANS_RATIO            52   //0.1
#define REG_PARAM_LOAD_IMP               53   //ohm
#define REG_PARAM_SWITCHBOX1_DT_L        54
#define REG_PARAM_SWITCHBOX1_DT_H        55
#define REG_PARAM_SWITCHBOX2_DT_L        56
#define REG_PARAM_SWITCHBOX2_DT_H        57
#define REG_PARAM_SWITCHBOX3_DT_L        58
#define REG_PARAM_SWITCHBOX3_DT_H        59
#define REG_PARAM_FAULT_MASK             60
#define PARAM_REG_END                    60
#define NVD_REG_END                      60
/*---------nvd registers end-----------*/

/* cmd registers group */
#define CMD_REG_START                    61
#define REG_CMD_L                        61
#define REG_CMD_H                        62
#define CMD_REG_END                      62
/* status registers group */
#define STATUS_REG_START                 63
#define REG_STATUS_0_L                   63
#define REG_STATUS_0_H                   64
#define REG_STATUS_1_L                   65
#define REG_STATUS_1_H                   66
#define REG_STATUS_2_L                   67
#define REG_STATUS_2_H                   68
#define REG_STATUS_3_L                   69
#define REG_STATUS_3_H                   70
#define REG_STATUS_4_L                   71
#define REG_STATUS_4_H                   72
#define REG_STATUS_5_L                   73
#define REG_STATUS_5_H                   74
#define REG_STATUS_6_L                   75
#define REG_STATUS_6_H                   76
#define REG_STATUS_7_L                   77
#define REG_STATUS_7_H                   78
#define STATUS_REG_END                   78
/* data registers group */
#define DATA_REG_START                   79
#define REG_DATA_PULSE_VOL               79   //0.1kV
#define REG_DATA_PULSE_CUR               80   //0.1A
#define REG_DATA_PULSE_FREQ              81   //1Hz
#define REG_DATA_PULSE_WIDTH             82   //0.1us
#define REG_DATA_CHARGE_VOL              83   //0.1V
#define REG_DATA_CHARGE_CUR              84   //0.1A
#define REG_DATA_HEATER_VOL              85   //0.1V
#define REG_DATA_HEATER_CUR              86   //0.1A
#define REG_DATA_MMAG_VOL                87   //0.1V
#define REG_DATA_MMAG_CUR                88   //0.1A
#define REG_DATA_CMAG_VOL                89   //0.1V
#define REG_DATA_CMAG_CUR                90   //0.1A
#define REG_DATA_WATER_TEMP_1            91   //0.01deg
#define REG_DATA_WATER_TEMP_2            92   //0.01deg
#define REG_DATA_WATER_TEMP_3            93   //0.01deg
#define REG_DATA_WATER_TEMP_4            94   //0.01deg
#define REG_DATA_WATER_FLOW_1            95   //0.01L/min
#define REG_DATA_WATER_FLOW_2            96   //0.01L/min
#define REG_DATA_WATER_FLOW_3            97   //0.01L/min
#define REG_DATA_WATER_FLOW_4            98   //0.01L/min
#define REG_DATA_HVOL_TCT_L              99   //sec
#define REG_DATA_HVOL_TCT_H              100   //sec
#define REG_DATA_LVOL_TCT_L              101   //sec
#define REG_DATA_LVOL_TCT_H              102   //sec
#define REG_DATA_HVOL_CT_L               103   //sec
#define REG_DATA_HVOL_CT_H               104   //sec
#define REG_DATA_LVOL_CT_L               105   //sec
#define REG_DATA_LVOL_CT_H               106   //sec
#define REG_DATA_PREHEAT_CTD             107   //sec
#define REG_DATA_FIRE_CT                 108
#define REG_DATA_SYSTIME_L               109   //sec
#define REG_DATA_SYSTIME_H               110   //sec
#define DATA_REG_END                     110
/*
*/
#define REG_NUMBER                       111
#define NVD_REG_NUMBER                   61
/*
*/
extern uint16_t reg_table[REG_NUMBER];
extern uint16_t nvd_reg_table[][3];
void nvd_reg_reset();
void nvd_reg_limit(int addr, uint16_t data);
void nvd_reg_limit(int addr, int16_t data);
void reg16_write(int addr, uint16_t data);
void reg32_write(int addr, uint32_t data);
void reg48_write(int addr, uint48_t data);
void reg64_write(int addr, uint64_t data);
uint16_t reg16_read(int addr);
uint32_t reg32_read(int addr);
uint64_t reg48_read(int addr);
uint64_t reg64_read(int addr);
